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KM4232W259A cmos window ram rev.0 (august 1997) the KM4232W259A is a 1m byte dual ported dram array with added features that accelerate graphic operations in a gui environment. a 256-bit internal bus allows transferring up to 32 bytes of data on a single chip. all necessary features present to support fully functional scroll and aligned block-move graphic operations. the 16-bit serial output port is comprised of two 128-byte serial registers. this allows relaxed system timing and full cpu access while the registers are being emptied to the display. to enhance the block transfer performance for windows-based operations, the KM4232W259A also provides block write mode of 8-columns which allows 32-bytes maximum of block data transfer at a time. a choice of 2-colors can be used in any com- bination of foreground and background mixing.(e.g. for mono- chrome and color text expansion) this operation is useful for graphic fill and text operations. a combination of mixed modes(see truth table) defined by the cas falling edge is also supported. this performance enhance- ment feature allows system designers to change the mode of operation on the fly within ultra fast page cycle time. ? 1m byte frame-buffer on a single chip ? 2.1 g byte/second internal bus : -. fast window drawing operations -. fill at up to 2.1 g byte/second -. aligned bitblt at up to 0.64 g byte/second ? 8-column block write with bit and byte masking capability ? 267 m bytes/second cpu read/write data path : -. fast image read/writes -. 15ns ultra fast page mode( t upc ) with edo ? 4 each be and oe for byte-write/read control ? dual 128 byte split serial register -. dual buffers relax system timing -. 83mhz serial clock frequency ? 5.0v 10% supply voltage ? ttl i/o level compatible ? 120-pin pqfp general description features pin names pin name pin function sc serial clock se serial enable sq 0 -sq 15 serial data output be 0 - 3 byte enable oe output enable ras row address strobe cas column address strobe dsf 0, 1, 2 special function pins w 0 /dq 0 ~ w 31 /dq 31 data write mask/ input-output a 0 ~ a 8 address inputs nc (no connection) v cc power v ss ground key timing parameters speed parameter -50 -60 ram read/write & block ultra fast page cycle time( t upc ) 15ns 20ns ras access time( t rac ) 50ns 60ns cas access time( t cac ) 12ns 12ns ras cycle time( t rc ) 90ns 110ns sam cycle time( t scc ) 12ns 14ns sam access time( t sca ) 10ns 13ns se access time( t sea ) 12ns 12ns i dd 1 : ram op. current 180ma 160ma i dd 2 : stand-by current 10ma 10ma i dd 1a : ram & sam op. current 210ma 190ma i dd 2a : sam op. current 50ma 45ma performance graphic operations cycle peak performance 10-pixel vector ufw 2.96 m vector/sec 7 x 9 character draw ufw 1.5 m character/sec fill ufbw8 2.1 g byte/sec bitblt(vertical scroll) ufbr/ufbwl 0.45 g byte/sec samsung electronics co.ltd. reserves the right to change products and specifications without notice.
KM4232W259A cmos window ram rev.0 (august 1997) pin configuration (top view) n.c n.c v ss sq1 sq0 v cc dq23 dq22 v ss dq21 dq20 v cc dq19 dq18 v ss dq17 dq16 v cc cas ras v cc dq7 dq6 v ss dq5 dq4 v cc dq3 dq2 v ss dq1 dq0 v ss v ss n.c n.c 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 120 pin pqfp s q 1 0 s q 1 1 v c c s q 1 2 s q 1 3 v s s v c c s q 1 4 s q 1 5 v c c v c c v s s v s s v s s n . c s q 7 s q 6 v c c v s s s q 5 s q 4 v c c s q 3 s q 2 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 n.c n.c v ss sq9 sq8 v cc dq31 dq30 v ss dq29 dq28 v cc dq27 dq26 v ss dq25 dq24 v cc sc se v cc dq15 dq14 v ss dq13 dq12 v cc dq11 dq10 v ss dq9 dq8 v ss v ss n.c n.c 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 b e 3 b e 1 o e d s f 0 d s f 1 d s f 2 n . c v s s v s s v s s v c c v c c a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 n . c b e 0 b e 2 9 7 9 8 9 9 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 figure 1. pin configuration
KM4232W259A cmos window ram rev.0 (august 1997) pin description *1 edo : extended data out symbol type description sc input serial clock : clock input to the serial address counter for the sam registers. the serial access is initiated from sc rising edge. output data is held until the next clock rising edge. se input serial port enable : se enables the serial output buffers. sq 0 - sq 15 output serial output : output pins of the 128 x 16 serial data register. be 0 - 3 input byte enable : these signals enables the random output buffer during read operation or the write driver during write operation. they are latched on the falling edge of cas . be 0 controls w 0 /dq 0 - w 7 /dq 7 . oe input output enable : enables the random output buffer when dropped low after cas goes low. otherwise the output is in a high-z state. on the falling edge of ras , oe =high indicates new mask data will be used for the operation. if oe =low, previously loaded mask data is used. ras input row address strobe : it acts as a master chip enable clock, also serves as a clock to latch the row address(a 0 - a 8 ). it also latches the mask data for bit plane mask when oe is high at ras falling edge. cas before ras refresh mode is available if falling edge of ras is preceded by cas =low. cas input column address strobe : used as a clock, which latches the column address(a 0 - a 8 ) and determines the functionality of mixed mode by monitoring dsf status. it can also initiate the read(edo*1) or write access to the selected words and transfer the selected data(256 bits) to the sam register. dsf0, 1, 2 input special function select : the dsf0, 1, 2 data latched by cas falling edge is used to indicate which special functions, block write, internal move, lcr, lmr split read transfer, ultra fast page mode read(edo) and write cycles, are going to be performed. w 0 /dq 0 - w 31 /dq 31 input output input and output pin to the ram : these pins carry read, write or mask data, depending upon the type of cycle. refer to ras and cas control cycles truth tables. a 0 - a 8 input address input : the KM4232W259A utilizes a multiplexed addressing method for selecting one word among 256k words of memory cells, 9 row addresses and 9 column addresses are latched by the ras and cas falling edges. some address pins can be used as control signals in particu- lar cycles(e.g. a 0 for lmr cycle, a 0 , a 1 for lcr, ufbw8, srt/srtr cycles, and a 0 and a 1 can address the latches during ufbr, ufbwl cycles).
KM4232W259A cmos window ram rev.0 (august 1997) c o l u m n d e c o d e r ( 5 1 2 ) dram bit 31 dram bit 30 dram bit 29 dram bit 2 dram bit 1 the window ram(wram tm ) can be divided into four major functional blocks(refer to block diagram). the dram array orga- nized as 32 (512 x 512) bit planes, the serial access mem- ory(sam), the read/write control blocks, and the color registers and data latches block. the wram tm cycles can be divided into two major categories, external data transfer cycles and internal data transfer cycles. functional description row decoder (512) dram bit 0 512 x 512 array (32 each) b i t l i n e s e n s e a m p s ( 5 1 2 ) i/o s/a, wdrv row address column address refresh counter load block control load block dest(2 bits) 8 8 latch 0 latch 1 latch 2 latch 3 color 0 color 1 block sam array 8 x 8 x 32 serial register control counter 2 : 1 m u x 16 16 16 serial data sq0 ~ 15 sc se b e 2 b e 0 write block control (ras enable, mux) write block source(2 bits) address buffer 8 a 0 ~ a 8 32 w/dq 0 ~ 31 data buffer 2 32 256 256 256 256 9 9 9 8 : 1 mux 256 r a s b e 1 o e b e 3 d s f 0 c a s d s f 2 d s f 1 9 figure 2. block diagram
KM4232W259A cmos window ram rev.0 (august 1997) ras control cycles truth table notes : 1. oe = 1 updates mask register content. oe = 0 uses previously loaded mask data. 2. = byte control(refer to byte enable truth table). cas #2 ras #1 mnemonic code function be 3 - 0 cas oe dsf2 dsf1 dsf0 ra 8 - 0 w 31 - 0 x 0 x x x 0 x x rst reset cycle x 0 x x x 1 x x cbr cbr refresh (note 2) 1 0/1 (note 1) x x 0 row wpb mask rw/ror new row initiation for any rw cycle, ras only refresh x 1 0/1 (note 1) x x 1 x wpb mask vendor specific mode byte enable truth table cas #2 operation be 0 0 1 byte read/write enable(dq 0 ~ dq 7 ) byte read/write disable(dq 0 ~ dq 7 ) be 1 0 1 byte read/write enable(dq 8 ~ dq 15 ) byte read/write disable(dq 8 ~ dq 15 ) be 2 0 1 byte read/write enable(dq 16 ~ dq 23 ) byte read/write disable(dq 16 ~ dq 23 ) be 3 0 1 byte read/write enable(dq 24 ~ dq 31 ) byte read/write disable(dq 24 ~ dq 31 ) reset cycle after reset cycle color register 0, 1 reset to "0" mask register reset to "1" : non-masking mode sam transfer counter reset to "0" : address the first row of sam(first sam)
KM4232W259A cmos window ram rev.0 (august 1997) cas control cycles truth table notes : 1. lmr cycle always updates mask register content. wi=1 enables write to bit plane i, wi=0 disables(masks) write to bit plane i 2. = byte control(refer to byte enable truth table). 3. wi(i=0, ...., 31) performs byte masking during ufbwl and ufbw8 cycles. wi =1 enables byte write to byte i. wi =0 disables (masks) byte write to byte i. 4. di(i =0, ...., 31) selects either color register 0(c 0 ) or color register 1(c 1 ) to be written into dram. 5. ca 1 =0 accesses color register 0, ca 1 =1 accesses color register 1. cas #2 mnemonic code function be 3 - 0 (note 2) dsf2 dsf1 dsf0 ca w 31 /dq 31 - w 0 /dq 0 8 7 6 5 4 3 2 1 0 x x 1 1 0 0 1 1 x x x x x x x 0/1 0 x x x x x x x x 1 pixel color data mask data(wpb) lcr lmr load color reg. 0 or 1 (note 5) load mask reg. (note 1) x 0 0 0 x 0 0 x 0 1 x 1 0 x 1 1 x x x x x x x x x x x x x x x x ufbr dram to latch 0 dram to latch 1 dram to latch 2 dram to latch 3 0 1 1 x 0 0 x 0 1 x 1 0 x 1 1 ufbwl (note 3) latch 0 to dram latch 1 to dram latch 2 to dram latch 3 to dram 0 0 1 x 0 0 x 0 1 x 1 0 x 1 1 ufbw8 (note 3) (note 4) from color reg. 0 to dram from color reg. 1 to dram c 0 (di=0), c 1 (di=1) to dram c 0 (di=1), c 1 (di=0) to dram x x 0 0 1 1 0 0 x 0 0 x 0 1 x x x x x x x x srt srtr split read transfer split read transfer with sam pointer reset 1 1 0 d out(31~0) ufr ultra fast page read cycle 1 1 1 d in(31~0) ufw ultra fast page read cycle column address column address column address column address column address column address column address column address column address column address column address column address column address column address column address column address byte mask byte mask byte mask col reg. select col reg. select
KM4232W259A cmos window ram rev.0 (august 1997) absolute maximum ratings* note : permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating co n- ditions for extended periods may affect device reliability. parameter symbol rating unit voltage on any pin relative to vss v in , v out -1.0 to +7.0 v voltage on v cc supply relative to vss v cc -1.0 to +7.0 v storage temperature t stg -55 to +150 c power dissipation p d 1.2 w short circuit output current i os 50 ma dc operating conditions (voltage reference to v ss , t a = 0 to 70 c) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 0 0 0 v input high votlage v ih 2.4 - 6.5 v input low voltage v il -1.0 - 0.8 v dc operating characteristics (recommended operating conditions unless otherwise noted) * real values are dependent on output loading and cycle rates. specified values are obtained with the output open( se = oe =v ih ). i dd is specified average current ; in i dd 1, i dd 3, address transition once while ras =v il . in the i dd 5, i dd 6, i dd 7 address transition should be changed only once while cas =v ih . sam standby condition ; se 3 v ih , sc v il or 3 v ih . parameter(ram port) sam port symbol speed unit -50 -60 operating current* ( ras and cas cycling at t rc =min) standby i dd 1 180 160 ma active i dd 1a 210 190 ma standby current ( ras =v ih , cas =v ih ), dsf 0 ~ 2=v il standby i dd 2 10 10 ma active i dd 2a 50 45 ma ras only refresh current* ( cas =v ih , ras cycling at t rc =min) standby i dd 3 180 160 ma active i dd 3a 210 190 ma cas -before- ras refresh current* ( ras and cas cycling at t rc =min) standby i dd 4 180 160 ma active i dd 4a 210 190 ma ultra fast page mode current (lcr, lmr, rcr, rmr, ufr and ufw cycles)* ( ras =v il , cas cycling at t upc =min) standby i dd 5 190 170 ma active i dd 5a 220 200 ma ultra fast page mode current* (ufbwl and ufbw8 cycles) ( ras =v il , cas cycling at t upc =min) standby i dd 6 220 200 ma active i dd 6a 240 220 ma ultra fast page mode current* (ufbr, srt and srtr cycles) ( ras =v il , cas cycling at t upc =min) standby i dd 7 220 200 ma active i dd 7a 240 220 ma
KM4232W259A cmos window ram rev.0 (august 1997) ac operating conditions (voltage reference to v ss , t a = 0 to 70 c) parameter unit ac input levels v ih /v il =3.0v/0.0v output measurement reference level 1.4v input rise and fall time t r / t f =2ns/2ns capacitance (v cc = 5v, t a = 25 c, f = 1mhz) parameter symbol min. max. unit input capacitance (a 0 ~ a 8 ) c in1 3 6 pf input capacitance( ras , cas , be 0-3 , oe , se , sc, dsf 0-2 ) c in2 3 6 pf input/output capacitance (w 0 /dq 0 ~ w 31 /dq 31 ) c dq 3 7 pf output capacitance (sq 0 - 15 ) c sq 3 7 pf input/output current (recommended operating conditions unless otherwise noted) parameter symbol rating rating unit input leakage current(any input 0v v in 6.5v, all other pins not under test=0 volts). i il -10 10 ua output leakage current(data out is disabled, 0v v out 6.5v) i ol -10 10 ua output high voltage level (ram i oh =-2ma, sam i oh =-2ma) v oh 2.4 - v output low voltage level (ram i ol =2ma, sam i ol =2ma) v ol - 0.4 v
KM4232W259A cmos window ram rev.0 (august 1997) ac characteristics (0 c t a 70 c, v cc =5v 10%, see notes 1 and 2) parameter symbol -50ns -60ns unit notes min max min max access time from cas t cac 12 12 ns 3, 5, 6 access time from cas precharge t cpa 20 25 ns 3 ultra fast page mode cycle time t upc 15 20 ns access time from column address t aa 22 27 ns 3, 9 access time from output enable t oea 12 12 ns access time from ras t rac 50 60 ns 3, 5, 9 access time from sc t sca 10 13 ns 4 access time from se t sea 12 12 ns 4 transition time(rise and fall) t t 2 30 2 30 ns 2, 12 random read or write cycle time t rc 90 110 ns ras pulse width t ras 50 10k 60 10k ns ras pulse width(ultra fast page mode) t rasp 50 100k 60 100k ns ras to cas delay time t rcd 20 38 25 48 ns 5 ras to column address delay time t rad 12 28 15 33 ns 9 ras hold time t rsh 15 15 ns ras precharge time t rp 35 40 ns ras precharge to cas hold time t rpc 10 10 ns cas hold time t csh 45 60 ns cas precharge time(ultra fast page mode) t cp 5 8 ns cas pulse width t cas 6 10k 8 10k ns cas setup time(cbr refresh) t csr 5 5 ns cas hold time(cbr refresh) t chr 10 10 ns cas to output in low-z t clz 5 5 ns 3, 10 cas to ras precharge time t crp 5 5 ns row address hold time t rah 6 8 ns row address setup time t asr 0 0 ns column address hold time t cah 0 0 ns column address setup time t asc 7 8 ns column address to ras lead time t ral 22 30 ns data hold time t dh 0 0 ns data setup time t ds 7 8 ns write per bit mask data hold t mh 8 8 ns write per bit mask data setup t ms 0 0 ns read-write cycle time t pcrw 35 35 ns output buffer turn-off delay from cas t off 3 7 3 7 ns 7
KM4232W259A cmos window ram rev.0 (august 1997) ac characteristics (continued) parameter symbol -50ns -60ns unit notes min max min max dsf hold time referenced to ras t rfh 8 8 ns dsf setup referenced to ras t fsr 0 0 ns dsf hold time referenced to cas t cfh 0 0 ns dsf setup referenced to cas t fsc 7 8 ns data to cas delay t dzc 0 0 ns output buffer turn-off delay from oe t oez 3 7 3 7 ns 7 output buffer turn-on delay from oe t oeo 5 5 ns 3, 10 oe to data input delay t oed 7 7 ns output data hold time t doh 3 3 ns oe precharge time t oep 5 5 ns oe hold referenced to ras t orh 8 8 ns oe setup referenced to ras t ors 0 0 ns oe hold time referenced to cas t ohc 0 0 ns 8 oe setup referenced to cas t osc 20 17 ns 8 oe to cas hold time to see vaild output t och 5 5 ns 8 cas to oe hold time to hide the output t cho 5 5 ns 8 output buffer turn-off delay from be when be is high at the falling edge of cas t bez 3 7 3 7 ns 7 be hold referenced to cas t cbh 0 0 ns be setup referenced to cas t bsc 7 8 ns refresh period(512 cycle) t ref 17 17 ms sc cycle time t scc 12 14 ns sc precharge(sc low ime) t scp 4 5 ns sc pulse width(sc high time) t sc 4 5 ns serial out buffer turn-off from se t sez 3 6 3 6 ns 7 serial out buffer turn-on from se t seo 5 5 ns 4, 10 se precharge time t sep 5 5 ns serial output hold time from sc t soh 3 3 ns cas to sc setup(srt cycle) t css 6sc 112sc 6sc 112sc clk rising 14 cas to sc setup(srtr and 1st srt cycle) t srtr 15 18 ns 11 sc hold referenced to cas (srtr and first srt cycle) t cstr 4 4 ns 11 ras to sc delay (srtr cycle and first srt cycle) t rsd 50 60 ns 11
KM4232W259A cmos window ram rev.0 (august 1997) notes : 1. an initial pause of 200us is required after power-up followed by any 8 ras , 8 sc cycles before proper device operation is achieved( oe & se =high). if the internal refresh counter is used, a minimum of 8 cas -before- ras initialization cycles are required instead of 8 ras cycles. a reset cycle must be executed right after the 8 initialization cycles to ensure proper device operation. a reset cycle should be executed only right after power-up. it should never be executed during operation because this would bring the wram back to the initial state right after power-up. 2. v ih (min) and v il (max) are reference levels for measuring tim- ing of input signals. transition times are measured between v ih (min) and v il (max), and are assumed to be 2ns for all inputs. 3. ram port outputs are measured with a load equivalent to 1 ttl loads and 50pf. d out comparator level : v oh /v ol =1.4v 4. sam port outputs are measured with a load equivalent to 1 ttl loads and 30pf. d out comparator level : v oh /v ol =1.4v 5. operation within the t rcd (max) limit insures the t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 6. assumes that t rcd 3 t rcd (max). 7. the parameters t off, t oez, t bez and t sez define the time at which the output achieves the open circuit condition. t off is determined by the rising edge of ras or cas whichever comes later. 8. for a reference, t osc and t ohc is used to write data input in read-write cycle. t och and t cho is used to see or hide the output in ultra fast page read with oe controlled cycle. ac characteristics (continued) 9. operation within the t rad (max) limit insures that t rcd (max) can be met . t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa. 10.the parameters t oeo , t seo , and t clz define the time at which the output achieves low-z state. 11. t cstr , t srtr , t rsd only apply to the srtr cycle and the very first srt cycle after power up(i.e. the very first srt cycle after power up is equivalent to a srtr cycle). 12. operating input condition. input signals transition levels are from 0.0v to 3.0v for ac testing. all timing levels are referenced from v il (max) and v ih (min) with transition time of 2.0ns. 13.power recommended be applied to the ras and oe input signals to pull them "high" before or at the same time as the v cc supply is turned on. 14.transfer and serial read operation can't be performed at the same sam row simultaneously. t t 0.8v t t 2.4v 0.0v 3.0v
KM4232W259A cmos window ram rev.0 (august 1997) basic features/functional description block write of 8-column : bw8 bw8 examples purpose to transfer a large block of data (32 bytes max.), which is deter- mined by the 32-bit color register(s) data, to all or any given 32 dram plane(s). the bw8 mode is sampled by cas falling edge. functional description - each 32-bit of the color register(s) data corresponds to each 32 dram planes. example : d0 corresponds to plane #0 of dram array. - a group of column data bits(8 columns) can be written onto any specific 32 dram plane(s). - any given 32 dram plane(s) can be "masked out" through the wpb function for specific plane(s) for protection or overlay application purposes. - byte masking(pixel masking for 8bpp system) function is also provided. summary of 1m byte wram tm basic features and benefits features 256k x 32 wram benefits block write 8 columns high speed fill, clear, text with color registers. maximum 32 byte data transfers(e.g. for 8bpp ; 32 pixels) with plane and byte masking func- tions mixed modes lcr + ufbw8 + ufbw8 + .... all cas falling edge defined cycles(see truth table) can be operated in mix modes within ultra fast page cycles. color registers 2 foreground and background color data in any combination mask register 1 write-per-bit capability(bit plane masking) latches 4 aligned bitblt, scroll data bus(internal) 256 high bandwidth for scroll, fill, bitblt, road transfer(with 15ns r/w) split sam (2) x(128 bytes) display interface at low cost(read transfers only) row length 2048 bytes high speed vertical and horizontal drawing page cycle time for external write(s)/read(s) 15ns high speed i/o interface page cycle time for external write(s)/read(s) 15ns high performance gain for scroll, fill, bitblt, and read transfer operations refresh period 17ms display interface at low cost(read transfers only) interface async high speed vertical and horizontal drawing example#1(fill operation from 8bpp system) the following example will use a bw8 mode to fill two 1024 lines with red color only(assuming red color=10101010) display per 1 line requires (32) (bw8) each bw8 can transfer maximum 32 bytes ; 32 pixels(8bpp) in one write(15ns) transaction 1024 pixels bw8 bw8 bw8 bw8 bw8 bw8 .... #1 #2 #3 #4 #5 #32 pixel #0 .... (red) pixel #1 (red) pixel #31 (red) x x x
KM4232W259A cmos window ram rev.0 (august 1997) 1 1 1 1 0 0 0 0 #0 #2 #4 #6 #7 #5 #3 #1 1 1 1 1 1 1 1 data :8 columns b i t p l a n e d i r e c t i o n representing data per plane 1pixel the KM4232W259A wram has a total of 32 dram planes in bit plane direction which is comprised of a maximum of 4 pixels from the 1st column of data per dram. p i x e l # 0 p i x e l # 4 p i x e l # 8 p i x e l # 1 2 p i x e l # 1 6 p i x e l # 2 0 p i x e l # 2 4 p i x e l # 2 8 p i x e l # 1 p i x e l # 5 p i x e l # 9 p i x e l # 1 3 p i x e l # 1 7 p i x e l # 2 1 p i x e l # 2 5 p i x e l # 2 9 p i x e l # 2 p i x e l # 6 p i x e l # 1 0 p i x e l # 1 4 p i x e l # 1 8 p i x e l # 2 2 p i x e l # 2 6 p i x e l # 3 0 p i x e l # 3 p i x e l # 7 p i x e l # 1 1 p i x e l # 1 5 p i x e l # 1 9 p i x e l # 2 3 p i x e l # 2 7 p i x e l # 3 1 total of 32 pixels all in same red color ; 10101010 8 dram planes (7:0) 8 dram planes (15:8) 8 dram planes (23:16) 8 dram planes (31:24) 32 dram planes ( r e d = 1 0 1 0 1 0 1 0 ) ( r e d = 1 0 1 0 1 0 1 0 ) ( r e d ) ( r e d ) ( r e d ) figure 3. fill operation from 8bpp system each pixel is mapped from 8 dram planes in bit plane direction per 1 column
KM4232W259A cmos window ram rev.0 (august 1997) how color registers(0/1) ties to bw8 the color register(#0 or #1) should be loaded with the pixel color data(in this case, red color=10101010) from 32 i/o pins with a lcr cycle. cycles required for this operation : lcr(load color register 0 or 1) ufbw8 ufbw8 ufbw8 . . . . 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 b31 b0 msb red color red color red color red color lsb data for pixel# 3, 7, 11, 15, 19, 23, 27, 31 data for pixel# 2, 6, 10, 14, 18, 22, 26, 30 data for pixel# 1, 5, 9, 13, 17, 21, 25, 29 data for pixel# 0, 4, 8, 12, 16, 20, 24, 28 bit #0 of the color register(0 or 1) must tie to dram plane #0, bit #1 of the color register(0 or 1) must tie to dram plane #1, bit #31 of the color register(0 or 1) must tie to dram plane #31, . . . .
KM4232W259A cmos window ram rev.0 (august 1997) example #2 (pattern write operation from 8bpp system) the following example uses bw8 mode to write groups of pixel patterns(4 pixels per pattern write) across a partial scan line (for simplicity this example only uses 1 color register mode). assuming red : 10101010 (r) p i x e l # 0 p i x e l # 4 p i x e l # 8 p i x e l # 1 2 p i x e l # 1 6 p i x e l # 2 0 p i x e l # 2 4 p i x e l # 2 8 p i x e l # 1 p i x e l # 5 p i x e l # 9 p i x e l # 1 3 p i x e l # 1 7 p i x e l # 2 1 p i x e l # 2 5 p i x e l # 2 9 p i x e l # 2 p i x e l # 6 p i x e l # 1 0 p i x e l # 1 4 p i x e l # 1 8 p i x e l # 2 2 p i x e l # 2 6 p i x e l # 3 0 p i x e l # 3 p i x e l # 7 p i x e l # 1 1 p i x e l # 1 5 p i x e l # 1 9 p i x e l # 2 3 p i x e l # 2 7 p i x e l # 3 1 foreground data 8 dram planes (7:0) 8 dram planes (15:8) 8 dram planes (23:16) 8 dram planes (31:24) 32 dram planes r g g b figure 4. pattern write operation from 8bpp system green : 01111110 (g) blue : 10000001 (b) black : 00000000 (na) display na r g g b g g b na na na na na na na na r g g b ...... na r pixel # 12 4 1 2 3 5 6 7 8 9 10 11 13 14 15 16 17 18 19 0 .................... writes of group # pattern use byte masking use byte masking r g g b n a n a n a n a r g g b n a n a n a n a n a n a n a n a n a n a n a n a n a n a n a n a background data foreground data background data use byte masking "0" use byte masking "0" 1 2 3 4 5
KM4232W259A cmos window ram rev.0 (august 1997) how color registers(0/1) ties to bw8 the color register(#0 or #1) should be loaded with the pixel color data(in this case, red color=10101010) from 32 i/o pins with a lcr cycle. repeat the above steps to write na na na na pixel data(background data) cycles reguired for this operation : 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 b31 b0 msb blue color green color green color red color lsb data for pixel# 3, 7, 11, 15, 19, 23, 27, 31 data for pixel# 2, 6, 10, 14, 18, 22, 26, 30 data for pixel# 1, 5, 9, 13, 17, 21, 25, 29 data for pixel# 0, 4, 8, 12, 16, 20, 24, 28 color register #0 or #1 masking out pixel # < 15: 8 > and # < 31:20> use byte masking(8bpp=> pixel masking) function from bw8 mode at the falling edge of cas . in this bw8 cycle with byte masking, the 32-bit data write mask(w 0 -w 31 ) should be provided as follows. 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 w 31 w 0 msb lsb 1 => enable the byte write 0 => disable the byte write w<7:0> enable the write buffers ; allow pixel<7:0> not to be masked. w<19:16> enable the write buffers ; allow pixel<19:16> not to be masked. w<15:8> & w<31:20> disable the write buffers ; allow pixel #<15:8> & #<31:20>> to be masked. each of these bits can be used to mask("0") or not mask("1") the whole 8-bit pixel data. use bw8 mode to write r g g b pixels data(foreground data). (foreground r g g b) - lcr - byte mask info // ufbw8 (background na na na na) - lcr - byte mask info // ufbw8
KM4232W259A cmos window ram rev.0 (august 1997) example #3 : (random pattern write operation from 8bpp system) the following example uses bw8 mode to write a "red cross" across a portion of 3 scan lines with one color register ; (can also be done by using ultra fast write cycle for the "red cross" or with 2 color register mode for faster drawing). assuming red : 10101010 (r) p i x e l # 0 p i x e l # 4 p i x e l # 8 p i x e l # 1 2 p i x e l # 1 6 p i x e l # 2 0 p i x e l # 2 4 p i x e l # 2 8 p i x e l # 1 p i x e l # 5 p i x e l # 9 p i x e l # 1 3 p i x e l # 1 7 p i x e l # 2 1 p i x e l # 2 5 p i x e l # 2 9 p i x e l # 2 p i x e l # 6 p i x e l # 1 0 p i x e l # 1 4 p i x e l # 1 8 p i x e l # 2 2 p i x e l # 2 6 p i x e l # 3 0 p i x e l # 3 p i x e l # 7 p i x e l # 1 1 p i x e l # 1 5 p i x e l # 1 9 p i x e l # 2 3 p i x e l # 2 7 p i x e l # 3 1 8 dram planes (7:0) 8 dram planes (15:8) 8 dram planes (23:16) 8 dram planes (31:24) 32 dram planes w w w w figure 5. random pattern write operation from 8bpp system white : 11110000 (w) display w w w w w w w w r r r x w w w w ............... w w w w w r r r o l d c o l o r d a t a w w w w w w w w w w w w w w w w w w w w do not want to modify this pixel use byte masking "0" use byte masking "0" r w w w w r r r r r r r r w w w ............... w w w w w w w w w r r r w w w w w ............... w pixel # 12 4 1 2 3 5 6 7 8 9 10 11 13 14 15 16 ....... 31(for scan #1) 0 44 36 33 34 35 37 38 39 40 41 42 43 45 46 47 48 ....... 63(for scan #1) 32 76 68 65 66 67 69 70 71 72 73 74 75 77 78 79 80 ....... 95(for scan #1) 64 red : 10101010 (r) white : 11110000 (w)
KM4232W259A cmos window ram rev.0 (august 1997) load the color register(#0 or #1) with the following information : cycles reguired for this operation : lcr cycle for color register 0 byte masking information // ufbw8 -- use the same methodology to fill out "w" color data for pixel #<7:0> and #<31:12> on scan line #1. -- repeat the above steps for the next 2 scan lines of information. x x x x x x x x 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 b31 b0 msb red red red lsb data for pixel# 3, 7, 11, 15, 19, 23, 27, 31 data for pixel# 2, 6, 10, 14, 18, 22, 26, 30 data for pixel# 1, 5, 9, 13, 17, 21, 25, 29 data for pixel# 0, 4, 8, 12, 16, 20, 24, 28 color register #0 or #1 pixel # < 7: 0 > and # < 31:11> masked out use byte masking function bw8 mode(pixel masking for 8bpp system) to mask at the falling edge of cas ; 32-bit data write mask(w 0 -w 31 ) should be provided as follows. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 w 31 w 0 msb lsb 0 => disable the byte write 1 => enable the byte write this pixel masking data(byte masking data) should be done from bw8 cycle.
KM4232W259A cmos window ram rev.0 (august 1997) example #4 : (random pattern write operation from block write 2 color registers.) the following example uses bw8 mode to write a "red cross" across a portion of 3 scan lines with 2 color register. assuming red : 10101010 (r) white : 11111111 (w) display w w w w w w w w r r r x w w w w ............... w r w w w w r r r r r r r r w w w ............... w w w w w w w w w r r r w w w w w ............... w pixel # 12 4 1 2 3 5 6 7 8 9 10 11 13 14 15 16 ....... 31(for scan #1) 0 44 36 33 34 35 37 38 39 40 41 42 43 45 46 47 48 ....... 63(for scan #2) 32 78 70 65 66 67 71 72 73 74 75 76 77 79 80 81 82 ....... 95(for scan #3) 64 column 0 0 1 2 3 4 5 6 7 8 9 15 16 23 24 31 for scan line#1 column 1 column 2 column 3 column 4 column 5 column 6 column 7 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31 8 dram planes (7:0) 8 dram planes (15:8) 8 dram planes (23:16) 8 dram planes (31:24) din i cr0 (w) cr1 (r) w w w w r r r r source data of block write 0 1 2 3 4 5 6 7 8 9 10 16 24 31 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 6. example of bw8 using both color registers
KM4232W259A cmos window ram rev.0 (august 1997) 31 cycles required for this operaion : ? lcr cycle for color register 0(load white color) ? lcr cycle for color register 1(load read color) ? bw8 cycle with dini information date for scan line #1 din i 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 7. block diagram for bw8 with 2 color registers din 0 7 15 23 bit plane 0 din 0 din 4 din 8 din 12 din 16 din 20 din 24 din 28 cr0-0 write driver for bit plane 0 0-0 0-1 0-2 0-3 0-4 0-5 0-6 0-7 cr1-0 8 bit plane 1 cr0-1 write driver for bit plane 1 1-0 1-1 1-2 1-3 1-4 1-5 1-6 1-7 cr1-1 8 control bit plane 0-7
KM4232W259A cmos window ram rev.0 (august 1997) bit plane 31 mask operation the wram offers data masking in the following operation. - normal ultra fast page mode write cycle - block write mode - internal data block move from latch to dram mask register(wpb mask) loading the mask register can be performed in two ways : a) ras controlled. at the falling edge of ras , if oe ="1", then dqi will update mask register b) the cas - controlled lmr cycle also updates the mask register. each bit of the mask register (=mri) directly controls a corresponding bit plane. mr0 -> bit plan 0, mr1 -> bit plan 1 ..... mr31 -> bit plan 31. each bit enables write if "1", and disables write if "0" 512x512 internal byte mask a be 0 lmr or figure 8. block diagram of data path for all of write operation. pixel(byte) mask operation the operation is active for bw8 cycles or latch to dram cycle. each pixel can be masked by the value of dqi at cas falling edge. pixel0 - dq0, pixel1 - dq1, ...., pixel31 - dq31 dqi set to "0" disables pixel dqi set to "1" enables pixel byte enable control be 0-3 are sampled at cas falling edge. each byte enable line( be 0-3) disables the corresponding byte to be written if set to "1", if set to "0" each byte enable line enables the corre- sponding byte. be 0 controls bit plane 0:7 be 1 controls bit plane 8:15 be 2 controls bit plane 16:23 be 3 controls bit plane 24:31 dram array bit plane0 write driver x8 latch(x8) din buffer 0 dq 0 pin mask register color register (0 or 1) oe =h at ras bit plane 0 8 byte mask b c
KM4232W259A cmos window ram rev.0 (august 1997) in figure 8, "a" refers to a data path in a normal write mode ; "b" refers to block write ; "c" refers to an internal data block move. the block diagram illustrates how each wram plane relates to the corresponding register bit, and i/o pin. it also illustrates the data path for the following wram cycle : a) ultra fast page write cycle. b) block write cycle c) internal data block move cycle. ultra fast page mode write operation(bit plane mask) in figure 9, the example initializes mri data at the ras falling edge, after which the first write operation is executed with the bit plane mask information. change of mri data occurs through an lmr cycle, after which the new bit plane mask information is used for the second write operation. bw8 operation with pixel and bit plane mask figure 10 shows an example of block write 8 operation with one color register. to execute this operation, three cycles are per- formed sequentially : lcr cycle = load the color register data lmr cycle = load the bit plane mask data bw8 cycle = write the color register data to the dram array cell by pixel(byte) mask results of writing bit plane bit plane bit plane bit plane bit plane bit plane bit plane bit plane previous data 0 0 0 0 0 0 0 0 after 1st write 0 1 0 1 0 1 0 1 after 2nd write 1 1 1 1 0 1 0 1 figure 9. example of ultra fast page mode write operation(bit plane mask) note) : data not change ras cas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 load mask register 1st write lmr cycle 2nd write
KM4232W259A cmos window ram rev.0 (august 1997) column 0 0 1 2 3 4 5 6 7 8 9 10 11 10 11 15 16 23 24 26 28 30 31 timing sequence column 1 column 2 column 3 column 4 column 5 column 6 column 7 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 p25 p26 p27 p28 p29 p30 p31 din i cri cr0 cr0 cr0 cr0 cr1 cr1 cr1 cr1 figure 10. example of a bw8 operation with pixel and bit plane masking bit plane 0 d i n 0 d i n 4 d i n 8 d i n 1 2 d i n 1 6 d i n 2 0 d i n 2 4 write driver for bit plane 0 0-0 0-1 0-2 0-3 0-4 0-5 0-6 0-7 8 dini control bit plane 0-7 d i n 2 8 figure 11. block diagram for bw8 with pixel and bit plane mask cas dqi color register bit plane mask pixel mask information lcr lmr bw8 0 : mask 1 : no mask 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 1 2 3 4 5 9 6 7 8 10 11 16 24 31 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 mr i 0 : mask 1 : no mask pixel masking information bit plane masking information cr0-0 cr1-0 2 mr0 be 0 pixel masking information bit plane 1 write driver for bit plane 1 1-0 1-1 1-2 1-3 1-4 1-5 1-6 1-7 8 cr0-1 cr1-1 2 mr1 be 0 bit plane masking information
KM4232W259A cmos window ram rev.0 (august 1997) 31 a transfer operation is initiated when dsf 0 is "l", dsf 1 is "h", and dsf 2 is "l" at cas falling edge. 32 bytes of data transfers from dram to sam via a 256-bit internal buses within 15ns. when the transfer cycle is executed, the internal transfer pointer addresses the sam register that contains the data transferred from the ram. the column addresses a3 to a8 is the source address of the 32 bytes of data to be transferred to the sam register. the total sam size is 256 bytes, consisting of the 8 split register. each split register has a size of 32 bytes, which is the same as the internal bus size that fills it by one transfer cycle. to fill a whole sam register, 8 transfer cycles are required(figure 12). there are two types of transfer cycles : split read transfer cycle(srt) and split read transfer cycle with reset(srtr). the status of column address(a 0 ) at the falling edge of cas determines which type of transfer cycle(srt or srtr) is exe- cuted. ca 0 set to "0" selects an srt cycle and ca 0 set to "1" selects the srtr cycle. the transfer pointer which addresses the position in the sam register is a wrap-around counter and increments by 1 each transfer cycle. the sam register is reset to the first row posi- tion(the first row of the sam register) by the srtr cycle. on the first srt cycle after power up also performs the same reset function for the transfer pointer. figure 12. example of transfer cycle. cas sam transfer operation dram 512 x 512 bit plane 0 sam0 1st row 8th row . . . . sam register for bit plane 31 sam register for bit plane 0 31 total sam size : 8 rows x 8 columns x 32-bit plane = 256 bytes 8 column 256 8 1st 2nd 7th 8th srt or srt srtr 32 byte fill 1st row 32 byte fill 2nd row srt 32 byte fill 7th row srt 32 byte fill 8th row
KM4232W259A cmos window ram rev.0 (august 1997) serial read operation while transferring the dram data to sam, users can continu- ously read out sam data to the serial outputs from different rows of the sam. there are 16 serial outputs provided on the serial port. the on-chip 32 sam outputs which correspond the 32 dram bit planes, are shifted out through an on-chip 2:1 mux to the sq 0 -sq 15 pins(see figure 13) - a maximum of 2 pixels are read out from the wram at the same time for 8bpp system. - a maximum of 1 pixel is read out from the wram at the same time for 16bpp system. - a maximum of 1/2 pixel is read out from the wram at the same time for 32bpp system. the dram plane #<15:0> ties to one sq read, while the dram plane #<31:16> ties to another sq read on the next serial read cycle. the sam address pointer is the sam counter output. the sam counter is n-bit up-counter and wraps around by the internal operation, it is reset by the srtr cycle and 1st srt right after power-up. figure 13. functional block diagram of serial read sc sam register bit plane 0 bit plane pixel 0, 1 8 ~ 15 bit plane 0 ~ 7 pixel 4, 5 16 bit sam register bit plane 16 bit plane pixel 2, 3 24 ~ 31 bit plane 16 ~ 23 pixel 6, 7 16 bit 2 : 1 mux sam dout buffer 16 bit sdout 16-bit pixel 0, 1 pixel 2, 3 pixel 4, 5 pixel 6, 7 for 8bpp system
KM4232W259A cmos window ram rev.0 (august 1997) figure 14. example of sam operation sam counter(7-bit) 2nd row sc sam addr. 0 1 2 3 4 10 11 12 13 14 15 16 17 18 19 0 1 2 transfer 2nd row sqi 0 1 2 3 9 10 11 12 13 14 15 16 17 18 19 0 1 point addr. 1st row 1st row srtr cycle for 1st row srt cycle for 2nd row srtr cycle for 1st row ? ? ? ? ? 0 2 4 6 8 10 12 14 16 18 124 126 1 3 5 7 9 11 13 15 17 19 125 127 8-bit dram bit plane 0 (512 x 512) 8-bit dram bit plane 1 (512 x 512) 3rd row 8th row transfer counter 3 bit t srtr t css t srtr = 15ns(min) t cstr = 4ns(max) cas reset to initial sam counter
KM4232W259A cmos window ram rev.0 (august 1997) figure 14 illustrates the operation of the transfer cycle and the serial read cycle. the first cas cycle performs the fol- lowing : srtr cycle transfers the 8-bit column data of selected row to the 1st row of sam register. this cycle performs a reset operation to the transfer counter to address the first row, and resets the sam counter to address "0" of the first row of the sam register. the second cas cycle performs the following : the srt cycle transfers the 8-bit column data of selected row to the second row of sam register. when the srt cycle is performed, the t css is a minimum 6 sc cycle delay from srt cycle to the first sc clock for reading the data from that srt cycle. the third cas cycle performs the following : the srtr cycle resets the transfer counter and sam counter. the transfer counter points to the first row of sam, and the sam counter addresses "0" position of the 1st row of sam. when the srtr cycle is executed, t srtr and t cstr parameters must be satisfied in order to read the transferred data without delay(see figure 15). t srtr and t cstr are critical ac parameters to ensure the proper operation of srtr cycle. the difficulty of controlling t tsd and t tsl in a real-time read transfer cycle of vram. figure 15. example of system clock condition to perform srtr cycle [t srtr =15ns(min), t cstr =4ns(max)] sc cas sq 0-15 tap=0 t srtr = 15ns t sca = 10ns system example clock 0 1 2 3 4 5 6 7 t cstr = 4ns 10ns 5ns
KM4232W259A cmos window ram rev.0 (august 1997) ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t ras t rc t cp t rp t csh t rsh t rcd t cas t crp : don t care v oh - v ol - out valid data out read cycle(dram) timing diagrams addr v ih - v il - column(#2) row t ral t asr t rah t asc t cah (0-2) (0-3) w/dq (0~31) #2(read) t fsr t rfh t fsc t cfh * note ; #1, #2 : refer to "truth tables" #1 t bsc t cbh #2 t ors t orh #1 t ms t mh #1(wpb) t clz t oeo t off t rad t dzc t cac t oez t rac t oea t aa
KM4232W259A cmos window ram rev.0 (august 1997) data in ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t ras t rc t cp t rp t csh t rsh t rcd t cas t crp v oh - v ol - out write/load cycle(dram, color/mask register) timing diagrams(continued) addr v ih - v il - col-addr(#2) row t ral t asr t rah t asc t cah (0-2) (0-3) w/dq (0~31) #2(write) t fsr t rfh t fsc t cfh #1 t bsc t cbh #2 t ors t orh #1 t ms t mh t ds t rad open #1(wpb) t dh : don t care * note ; #1, #2 : refer to "truth tables"
KM4232W259A cmos window ram rev.0 (august 1997) t oeo t ds ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rasp t rp v oh - v ol - out read-write cycle(dram, color/mask register) timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) t ms t mh t ds open t dh row col-b #2 #1 #2 (write) #1 #1 data-in data-in (wpb) open open valid data out (a) t asr t rah t asc t cah col-a #2 t crp t rcd t cas t cp t cas t cp t cas t cp #2 #2 t cas t cp t ral t fsr t rfh t fsc t cfh #2 t ors t orh #2 (read) t dzc t oed col-c #2 col-d #2 #2 (read) #2 (write) t clz t cac t oea t oeo t oez t dzc t osc t ohc t osc t ohc valid data out (c) t cac t oea t oez t oed t dh t rac t aa t aa t clz t csh : don t care * note ; #1, #2 : refer to "truth tables" t pcrw t upc t pcrw t rsh t bsc t cbh #2
KM4232W259A cmos window ram rev.0 (august 1997) t dzc t mh t ms ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rasp t rp v oh - v ol - out ultra fast page read cycle(dram) timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) row #1 #2 #1 (wpb) open t asr t rah t asc t cah col-a #2 t crp t ral t fsr t rfh t fsc t cfh #1 t ors t orh #2 t och t oep t rac t aa t oez t csh t cp t cas t rsh t cp t cas t cp t upc t cas t rcd #2 #2 #2 col-b #2 col-c #2 #2 vaild data out(a) vaild data out(c) data out(b) t cac t clz t aa t cpa t cac t doh t oea t clz t cac t oeo t oez t off t aa t cpa t oea t rad : don t care * note ; #1, #2 : refer to "truth tables" t bsc t cbh
KM4232W259A cmos window ram rev.0 (august 1997) t ds t mh t ms ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rasp t rp v oh - v ol - out ultra fast page write/load cycle(dram, color/mask register) timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) row #1 #1 (wpb) t asr t rah t cah col-a #2 t crp t ral t fsr t rfh #1 t ors t orh t csh t cp t cas t rsh t cp t cas t cp t upc t cas t rcd col-b #2 col-c #2 data in data in data in t rad t dh #2 #2 #2 #2 #2 #2 t ds t dh t ds t dh : don t care * note ; #1, #2 : refer to "truth tables" t fsc t cfh t bsc t cbh t upc t asc
KM4232W259A cmos window ram rev.0 (august 1997) t oea t crp ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in v oh - v ol - out ultra fast page read-write/load cycle(dram, color/mask register) timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) #1 data data wpb in in valid data out(a) valid data out(b) valid d ata out(c) t rasp t rcd t cas t upc t cp t upc t cas t cp row col-a #2 col-c #2 col-b #2 col-e #2 col-d #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #1 t pcrw t upc t cas t cp t rsh t rp t ral t csh t cp t asr t rah t cah #1 t fsr t rfh t cfh t bsc t cbh #1 t ors t orh t osc t ohc t ms t mh t dzc t clz t oeo t cac t aa t cpa t cac t doh t aa t cpa t cac t doh t oez t ds t oed t dh t dh t ds t rac t aa : don t care * note ; #1, #2 : refer to "truth tables" t fsc t asc t rad
KM4232W259A cmos window ram rev.0 (august 1997) t doh t clz t ds t dh t crp ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in v oh - v ol - out ultra fast page write/load-read cycle timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) #1 wpb valid d ata out(d) valid data out(e) t rasp t rcd t cas t upc t cp t upc t cas t cp row col-a #2 col-c #2 col-b #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #2 #1 t upc t upc t cas t cp t rsh t rp t ral t csh t cp t asr t rah t cah #1 t fsr t rfh t cfh t fsc t bsc t cbh #1 t ors t orh t ms t mh t oea t off t oez t dzc t aa col-d #2 col-e #2 data in data in data in t ds t dh t ds t dh t oeo t cac t cac t aa : don t care * note ; #1, #2 : refer to "truth tables" t asc t rad t cas t cp t cas
KM4232W259A cmos window ram rev.0 (august 1997) t dzc ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rasp t rp v oh - v ol - out ultra fast page read(edo) with be controlled(dram, color/mask register) cycle timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) row #1 #2 open t asr t rah t asc t cah col-a (#2) t crp t ral t fsr t rfh t fsc t cfh #2 t rac t aa t csh t cp t cas t rsh t cp t cas t cp t upc t cas t rcd #2 col-b (#2) col-c (#2) vaild data out(a) vaild data out(c) t cac t clz t bez t doh t oea t clz t cac t oez t off t aa t cpa t rad t bsc t cbh t och t oeo : don t care * note ; #1, #2 : refer to "truth tables" t bsc t cbh t upc
KM4232W259A cmos window ram rev.0 (august 1997) t crp t och t dzc ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rasp t rp v oh - v ol - out ultra fast page read(edo) with oe controlled(dram, color/mask register) cycle timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) row #1 #2 t asr t rah t asc t cah col-a (#2) t ral t fsr t rfh t fsc t cfh #2 t rac t aa t csh t cp t cas t rsh t cp t cas t cp t upc t cas t rcd #2 col-b (#2) col-c (#2) vaild data vaild data t cac t oeo t cac t doh t oea t oez t oeo t oez t off t aa t cpa t rad t och #2 #2 #2 out(c) vaild data out(a) out(b) t clz t oez t oea t cac t cho t oep t oep t oea t bsc t cbh : don t care * note ; #1, #2 : refer to "truth tables" t upc
KM4232W259A cmos window ram rev.0 (august 1997) data in ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t ras t rc t cp t rp t csh t rsh t rcd t cas t crp v oh - v ol - out internal operation cycle(ufbr, ufbwl, ufbw8, srt, srtr) timing diagrams(continued) addr v ih - v il - col-addr(#2) row t ral t asr t rah t asc t cah (0-2) (0-3) w/dq (0~31) #2(write) t fsr t rfh t fsc t cfh #1 t bsc t cbh #2 t ors t orh #1 t ms t mh t ds t rad open #1(wpb) t dh : don t care * note ; #1, #2 : refer to "truth tables"
KM4232W259A cmos window ram rev.0 (august 1997) t ds t mh t ms ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rasp t rp v oh - v ol - out ultra fast page block read/write(latch)/write(color register) and split read timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) row #1 #1 (wpb) t asr t rah t asc t cah col-a #2 t crp t ral t fsr t rfh #1 t ors t orh t csh t cp t cas t rsh t cp t cas t cp t upc t cas t rcd col-b #2 col-c #2 #3 t rad t dh #2 #2 #2 #2 #2 #2 t ds t dh t ds t dh transfer and split read transfer with reset cycles( internal operation) #3 #3 : don t care * note ; #1, #2 : refer to "truth tables" t fsc t cfh t bsc t cbh t upc
KM4232W259A cmos window ram rev.0 (august 1997) t crp ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in : don t care v oh - v ol - out serial read and split read transfer cycle with reset cycle timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) * note ; #1, #2 : refer to "truth tables" t rasp t rcd t cas t upc t cp t upc #1 t upc t upc t rsh t rp t ral t csh t cp #1 t ors t orh t ds t dh (mixes with ultra fast page internal operations and write/load cycle) #1 #2 (srtr) #2 (srt) #2 (note a) t fsr t rfh t cfh t fsc #2 (note b) #2 (srtr) #2 t bsc t cbh #2 #1 data-in (note c) t ms t mh data-in sc v ih - v il - sq (0~15) v ih - v il - t ds t dh se v ih - v il - open wpb t sc t scc t scp t cstr t sca t soh t srtr t css t sez t sep t seo t sea ? ? ? t sca t sca t cstr t srtr inhibit rising transient tap =0(ls) inhibit rising transient tap =8(ls) tap =8(ls) tap =0(ls) (1st srt) row col-a #2 col-c #2 col-b #2 t asr t rah t cah t asc col-d #2 col-e #2 note a ; internal operation cycles ?? ufbr, srt, ufbwl, ufbw8.. note b ; write/load cycles ?? lcr, lmr, ufw note c ; data-in is normal data for lcr, lmr/byte masking data for ufbwl, ufbw8. tap=0(ms) t rad t rsd
KM4232W259A cmos window ram rev.0 (august 1997) t asc t crp ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in : don t care v oh - v ol - out serial read and split read transfer cycle timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) * note ; #1, #2 : refer to "truth tables" t rasp t rcd t cas t upc t cp t upc #1 t upc t pcrw t rsh t rp t ral t csh #1 t ors t orh t ds t dh (mixes with ultra fast page internal operations and read/write cycle) #1 #2 (srtr) #2 (srt) #2 (note a) t fsr t rfh t cfh t fsc #2 (note b) #2 (note c) #2 t bsc t cbh #2 #1 data-in (note d) t ms t mh data-in sc v ih - v il - sq (0~15) v ih - v il - se v ih - v il - t sc t scc t scp t cstr t sca t soh t srtr t css t sez t sep t seo t sea ? ? ? t sca t sca t cstr t srtr inhibit rising transient tap =0(ls) tap =8(ls) tap =8(ms) tap =0(ls) row col-a #2 col-c #2 col-b #2 t asr t rah t cah t asc col-d #2 col-e #2 note a ; ufbr, ufbwl, ufbw8, srt, lcr, lmr, ufw. note b ; read cycles ?? ufr note c ; internal operation cycles ?? ufbwl, ufbw8, srt, srtr. note d ; data-in is normal data for lcr, lmr and ufw cycles, byte masking data for ufbwl, ufbw8. #2 valid data t oeo t oez (note d) output t oea t cac t rsd tap=0(ms) t aa t cpa t ds t dh t oed inhibit rising transient t rad t cah t osc t ohc
KM4232W259A cmos window ram rev.0 (august 1997) t asc t crp ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in : don t care v oh - v ol - out serial read and the first srt, srtr cycle after power up timing diagrams(continued) addr v ih - v il - (0-2) (0-3) w/dq (0~31) * note ; #1, #2 : refer to "truth tables" t rasp t rcd t cas t upc t cp t upc #1 t upc t upc t rsh t rp t ral t csh #1 t ors t orh t ds t dh (mixes with ultra fast page internal operations and read cycle) #1 #2 (srtr) #2 (srt) #2 (note a) t fsr t rfh t cfh t fsc #2 t bsc t cbh #2 #1 data-in (note d) t ms t mh sc v ih - v il - sq (0~15) v ih - v il - se v ih - v il - t sc t scc t scp t cstr t sca t soh t srtr t css t sez t sep t seo t sea ? ? ? t sca t sca t cstr t srtr inhibit rising transient tap =0(ls) tap =8(ls) tap =8(ms) tap =0(ls) row col-a #2 col-c #2 col-b #2 t asr t rah t cah t asc col-d #2 col-e #2 note a ; ufbr, ufbwl, ufbw8, srt, lcr, lmr, ufw. note b ; read cycles ?? ufr note c ; internal operation cycles ?? ufbr, srt, srtr. note d ; data-in is only data for lcr, lmr and ufw cycles, byte masking data for ufbwl, ufbw8. #2 valid data output(d) t oea t cpa t rsd tap=0(ms) t aa t doh #2 (note b) #2 (note c) t cah 1st srt t dzc t cac t clz t oez inhibit rising transient t rad
KM4232W259A cmos window ram rev.0 (august 1997) ras v ih - v il - cas v ih - v il - dsf0 v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rc t rp v oh - v ol - out reset cycle timing diagrams(continued) addr v ih - v il - (0-3) w/dq (0~31) t chr t csr t cp t off t rpc t ras t fsr t rfh open : don t care dsf1~2= don t care
KM4232W259A cmos window ram rev.0 (august 1997) t crp ras v ih - v il - cas v ih - v il - dsf0 v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rc t rp v oh - v ol - out ras only refresh/new row initiation cycle timing diagrams(continued) addr v ih - v il - (0-3) w/dq (0~31) t crp t off t ras t asr t rah t rpc t asr t rah row row t fsr t rfh t fsr t rfh t ors t orh t ors t orh #1 #1 t ms t mh t ms t mh #1 wpb #1 wpb : don t care * note ; #1, #2 : refer to "truth tables" dsf1~2= don t care
KM4232W259A cmos window ram rev.0 (august 1997) ras v ih - v il - cas v ih - v il - dsf0 v ih - v il - be v ih - v il - oe v ih - v il - v ih - v il - in t rc t rpc v oh - v ol - out cas -before- ras refresh cycle timing diagrams(continued) addr v ih - v il - (0-3) w/dq (0~31) t chr t csr t cp t off t rpc t ras t fsr t rfh open t cp t rp dsf1~2= don t care : don t care t rp
KM4232W259A cmos window ram rev.0 (august 1997) valid data out ras v ih - v il - cas v ih - v il - dsf v ih - v il - be v ih - v il - oe v ih - v il - v oh - v ol - w/dq (0~31) t csh t rast t asc t rp t rsh t chr t cas t csr cas -before- ras refresh counter test cycle timing diagrams(continued) addr v ih - v il - t ral (0-2) (0-3) t aa open t oez don t care * note ; #2 : refer to "truth tables" #2 col t cah t cpt t fsc #2 t cfh t bsc #2 t cbh t ds data-in t dh t fsr t rfh read cycle t off t oea t cac t clz oe v ih - v il - v ih - v il - w/dq (0~31) write cycle t rad
KM4232W259A cmos window ram rev.0 (august 1997) package dimensions dimensions in millimeters 0.10 max 8 16.00 0.30 14.00 0.20 22.00 0.30 20.00 0.20 2.10 0.10 2.30 max 0.05 min 0.50 0.20 #1 0.15 + 0.10 - 0.05 1.25 1 . 2 5 0.20 + 0.10 - 0.05 0.50 #120 0.1 max

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